1. Field of the Invention
The present invention relates to the field of integrated circuit design and more particularly to simulation of complex logic circuits in which asynchronous time domains must coexist.
2. Background of the Invention
The relentless quest for performance has driven the clock frequency used in commercially available parts such as microprocessors to values expressed in hundreds of megahertz. Also, the dramatic increase of the level of integration that has been achieved in recent years, allowing millions of transistors on a single semiconductor chip, has enabled the possibility of actually merging functions requiring their own independent clocks that are not necessarily run in synchronism. Such a situation is typically encountered in the field of telecommunications when complex circuitry must interface at a very high-speed line e.g., an OC-192 telecommunication line close to 10 gigabit per second with a port of a switching function aimed at dispatching traffic at a network node. Because the speed of the line is set by international standards and the switch has its own set of requirements (such as interfacing simultaneously, through its many ports, different types of lines having to comply with various standards), the very densely integrated circuits designed today have to generally accommodate more than a single clock resulting in the presence of functional islands running asynchronously on the same piece of logic, a complete departure from the simple single-clocked way of implementing logic functions. Furthermore, the increasing complexity of electronic circuits has lead to development of independent building blocks, generally known as IP blocks, adapted to handle specific functions, that may be combined on a single circuit to perform high level functions. To be reusable, these IP blocks are described and tested independently of the hardware target technology, using high level language such as VHDL. Since these IP blocks are independent and may have been developed by different companies, they include their own clocks.
Most of the digital circuits that are commonly referred to as VLSI (Very Large Scale Integration) and are implemented into chips that may include millions of transistors, have, in practice, to house islands of logic operated from different time domains (i.e. clocked from asynchronous timing sources).
Since these logic islands need to interact and interface with each other in order to yield the global function for which the digital circuit is constructed, there is an increased risk to sample and propagate wrong data values from a first clock domain to a second clock domain.
FIG. 1 illustrates a part of a circuit design having two clock domains 100 and 110. The interface between these clock domains is handled by interface 120 having combinatory logic. The inputs I1 and I2 of this interface 120 correspond to the output of the latches 130 and 140 controlled by clock 1 of clock domain 100 and its output O1 is sampled by latch 150 controlled by clock 2 of clock domain 110. An example of this circuit design timing is shown on FIG. 2 where clock 1, clock 2 and interface output O1 behaviors are illustrated. Due to the delays introduced by interface 120, data sampled in latches 130 and 140 is not immediately available at the output of interface 120 after each clock 1 pulse. Thus, after clock 1 pulse n+1, the data sampled in latches 130 and 140 at time n is still available at the output of interface 120 before the data sampled in latches 130 and 140 at time n+1 becomes available, as depicted. Furthermore, there exists a particular state, noted X on the drawings, where the signal value is unstable. This unstable state is related to the time difference between paths contained in interface 120. Even if a single unstable state is represented per clock period on the drawing, several ones could exist. Sampling during an unstable state is avoided since it is meaningless. Thus, it is desirable to detect such unstable states in simulation to correct potential circuit design bugs. In this example, the first and third sampling at time m and m+2 respectively will not detect any lack of synchronism while the second sampling at time m+1 will detect an unstable state. As depicted, unstable state located in time period [n,n+1] has not been detected even though it represents a potential synchronism failure since sampling has been done close to and before it. It is to be noticed that unstable states are very short regarding a clock period and thus, the probability to sample a signal in an unstable period is very low in simulation. Therefore, the detection of unstable states requires very long simulations carried out by computer having important resources.
The most common approach to handle this problem is to simulate the circuit design, or a part of a circuit design, using its low level form, i.e. the circuit design mapped on the hardware target technology, taking into account the delays generated by the technology, and to perform an event driven simulation. However, this method requires a synthesis of the circuit design and a static timing analysis on placed/wired circuit design to get the proper circuit delays. Thus, the synchronism checking can only be done at the end of the circuit design cycle.
It is a broad object of the invention to remedy the shortcomings of the prior art as described herein above.
It is another object of the invention to disclose a method for detecting lack of synchronism in VLSI designs during high level simulation.
It is still another object of the invention to provide a method for detecting lack of synchronism in VLSI designs during high level simulation, adapted to be carried out by a small computer.
It is a further object of the invention to prevent the generation and propagation of wrongly sampled signals.
The accomplishment of these and other related objects is achieved by a method in a circuit design simulator for detecting lack of synchronism between at least two clock domains, each comprising a clock signal, wherein at least one clock domain of said at least two clock domains transmits data to at least one other clock domain of said two clock domains, comprising the step of applying a value representative of an unstable state to the input of said one other clock domain at each pulse of the clock of said at least one clock domain during a predetermined time, wherein lack of synchronism is detected when said at least one other clock domain samples said value representative of an unstable state.